Showing posts with label chip. Show all posts
Showing posts with label chip. Show all posts

Saturday, 2 January 2016

Optoelectronic microprocessors existing chip manufacturing

Optoelectronic microprocessors built using existing chip manufacturing. High-performance prototype means chipmakers could now start building optoelectronic chips.


Optoelectronic , microprocessors , chip, High-performance prototype, processors, MIT, computes electronically but uses light, Optical communication, optical filters, waveguides, light modulators, optical interfaces, photodetectors

Researchers have produced a working optoelectronic chip that computes electronically but uses light to move information. The chip has 850 optical components and 70 million transistors, which, while significantly less than the billion-odd transistors of a typical microprocessor, is enough to demonstrate all the functionality that a commercial optical chip would require.
Image: Glenn J. Asakawa


Scientia — Using only processes found in existing microchip fabrication facilities, researchers at MIT, the University of California at Berkeley, and the University of Colorado have produced a working optoelectronic microprocessor, which computes electronically but uses light to move information.


Optical communication could dramatically reduce chips’ power consumption, which is not only desirable in its own right but essential to maintaining the steady increases in computing power that we’ve come to expect.





Demonstrating that optical chips can be built with no alteration to existing semiconductor manufacturing processes should make optical communication more attractive to the computer industry. But it also makes an already daunting engineering challenge even more difficult.


“You have to use new physics and new designs to figure out how you take ingredients and process recipes that are used to make transistors, and use those to make photodetectors, light modulators, waveguides, optical filters, and optical interfaces,” says MIT professor of electrical engineering Rajeev Ram, referring to the optical components necessary to encode data onto different wavelengths of light, transmit it across a chip, and then decode it. “How do you build all the optics using only the layers out of a transistor? It felt a bit like an episode of ‘MacGyver’ where he has to build an optical network using only old computer parts.”


The project began as a collaboration between Ram, Vladimir Stojanović, and Krste Asanovic, who were then on the MIT Department of Electrical Engineering and Computer Science faculty. Stojanović and Asanovic have since moved to Berkeley, and they, Ram, and Miloš A. Popović, who was a graduate student and postdoc at MIT before becoming an assistant professor of electrical engineering at Colorado, are the senior authors on a paper in Nature that describes the new chip.


They’re joined by 19 co-authors, eight of whom were at MIT when the work was done, including two of the four first authors: graduate students Chen Sun and Jason Orcutt, who has since joined IBM’s T. J. Watson Research Center.


Powering down

The chip has 850 optical components and 70 million transistors, which, while significantly less than the billion-odd transistors of a typical microprocessor, is enough to demonstrate all the functionality that a commercial optical chip would require. In tests, the researchers found that the performance of their transistors was virtually indistinguishable from that of all-electronic computing devices built in the same facility.


Computer chips are constantly shipping data back and forth between logic circuits and memory, and today’s chips cannot keep the logic circuits supplied with enough data to take advantage of their ever-increasing speed. Boosting the bandwidth of the electrical connections between logic and memory would require more power, and that would raise the chips’ operating temperatures to unsustainable levels.


Optical data connections are, in principle, much more energy efficient. And unlike electrical connections, their power requirements don’t increase dramatically with distance. So optical connections could link processors that were meters rather than micrometers apart, with little loss in performance.


The researchers’ chip was manufactured by GlobalFoundries, a semiconductor manufacturing company that uses a silicon-on-insulator process, meaning that in its products, layers of silicon are insulated by layers of glass. The researchers build their waveguides — the optical components that guide light — atop a thin layer of glass on a silicon wafer. Then they etch away the silicon beneath them. The difference in refractive index — the degree to which a material bends light — between the silicon and the glass helps contain light traveling through the waveguides.





Conflicting needs

One of the difficulties in using transistor-manufacturing processes to produce optical devices is that transistor components are intended to conduct electricity, at least some of the time. But conductivity requires free charge carriers, which tend to absorb light particles, limiting optical transmission.


Computer chips, however, generally use both negative charge carriers — electrons — and positive charge carriers — “holes,” or the absence of an electron where one would be expected. “That means that somewhere in there, there should be some way to block every kind of [carrier] implant that they’re doing for every layer,” Ram explains. “We just had to figure out how we do that.”


In an optoelectronic chip, at some point, light signals have to be converted to electricity. But contact with metal also interferes with optical data transmission. The researchers found a way to pattern metal onto the inner ring of a donut-shaped optical component called a ring resonator. The metal doesn’t interact with light traveling around the resonator’s outer ring, but when a voltage is applied to it, it can either modify the optical properties of the resonator or register changes in a data-carrying light signal, allowing it to translate back and forth between optical and electrical signals.


On the new chip, the researchers demonstrated light detectors built from these ring resonators that are so sensitive that they could get the energy cost of transmitting a bit of information down to about a picojoule, or one-tenth of what all-electronic chips require, even over very short distances.


The new paper “certainly is an important result,” says Jagdeep Shah, a researcher at the U.S. Department of Defense’s Institute for Defense Analyses who, as a program director at the Defense Advanced Research Project Agency, initiated the program that sponsored the researchers’ work. “It is not at the megascale yet, and there are steps that need to be taken in order to get there. But this is a good step in that direction.”


“I think that the GlobalFoundries process was an industry-standard 45-nanometer design-rule process,” Shah adds. “I don’t think that there need be any concern that there’s any foundry that can’t make these things.”




– Credit and Resource –


Larry Hardesty | MIT News Office




Optoelectronic microprocessors existing chip manufacturing

Thursday, 10 December 2015

Microchip Design Boosts Performance

Skyscraper-style Microchip design boosts performance 1,000-fold


Chip, Skyscraper-style, boosts performance, Microchip, memory chips, processors , Nano-Engineered Computing Systems Technology, N3XT, electronics , Data

A multi-campus team led by Stanford engineers Subhasish Mitra and H.-S. Philip Wong has developed a revolutionary high-rise architecture for computing.






For decades, engineers have designed computer systems with processors and memory Microchips laid out like single-story structures in a suburb. Wires connect these chips like streets, carrying digital traffic between the processors that compute data and the memory microchips that store it.


But suburban-style layouts create long commutes and regular traffic jams in electronic circuits, wasting time and energy.


That is why researchers from three other universities are working with Stanford engineers, including Associate Professor Subhasish Mitra and Professor H.-S. Philip Wong, to create a revolutionary new high-rise architecture for computing.


In Rebooting Computing, a special issue of the IEEE Computer journal, the team describes its new approach as Nano-Engineered Computing Systems Technology, or N3XT.


N3XT will break data bottlenecks by integrating processors and memory like floors in a skyscraper and by connecting these components with millions of “vias,” which play the role of tiny electronic elevators. The N3XT high-rise approach will move more data, much faster, using far less energy, than would be possible using low-rise circuits.


“We have assembled a group of top thinkers and advanced technologies to create a platform that can meet the computing demands of the future,” Mitra said.


Shifting electronics from a low-rise to a high-rise architecture will demand huge investments from industry – and the promise of big payoffs for making the switch.


“When you combine higher speed with lower energy use, N3XT systems outperform conventional approaches by a factor of a thousand,” Wong said.


To enable these advances, the N3XT team uses new nano-materials that allow its designs to do what can’t be done with silicon – build high-rise computer circuits.


“With N3XT the whole is indeed greater than the sum of its parts,” said co-author and Stanford electrical engineering Professor Kunle Olukotun, who is helping optimize how software and hardware interact.


New transistor and memory materials

Engineers have previously tried to stack silicon chips but with limited success, said Mohamed M. Sabry Aly, a postdoctoral research fellow at Stanford and first author of the paper.


Fabricating a silicon microchip requires temperatures close to 1,800 degrees Fahrenheit, making it extremely challenging to build a silicon microchip atop another without damaging the first layer. The current approach to what are called 3-D, or stacked, microchips is to construct two silicon microchips separately, then stack them and connect them with a few thousand wires.


But conventional, 3-D silicon microchip’s are still prone to traffic jams and it takes a lot of energy to push data through what are a relatively few connecting wires.


The N3XT team is taking a radically different approach: building layers of processors and memory directly atop one another, connected by millions of electronic elevators that can move more data over shorter distances that traditional wire, using less energy. The N3XT approach is to immerse computation and memory storage into an electronic super-device.




The key is the use of non-silicon materials that can be fabricated at much lower temperatures than silicon, so that processors can be built on top of memory without the new layer damaging the layer below.


N3XT high-rise microchip’s are based on carbon nanotube transistors (CNTs). Transistors are fundamental units of a computer processor, the tiny on-off switches that create digital zeroes and ones. CNTs are faster and more energy-efficient than silicon processors. Moreover, in the N3XT architecture, they can be fabricated and placed over and below other layers of memory.


Among the N3XT scholars working at this nexus of computation and memory are Christos Kozyrakis and Eric Pop of Stanford, Jeffrey Bokor and Jan Rabaey of the University of California, Berkeley, Igor Markov of the University of Michigan, and Franz Franchetti and Larry Pileggi of Carnegie Mellon University.


Team members also envision using data storage technologies that rely on materials other than silicon, which can be manufactured on top of CNTs, using low-temperature fabrication processes.


One such data storage technology is called resistive random-access memory, or RRAM. Resistance slows down electrons, creating a zero, while conductivity allows electrons to flow, creating a one. Tiny jolts of electricity switch RRAM memory cells between these two digital states. N3XT team members are also experimenting with a variety of nano-scale magnetic materials to store digital ones and zeroes.


Just as skyscrapers have ventilation systems, N3XT high-rise chip designs incorporate thermal cooling layers. This work, led by Stanford mechanical engineers Kenneth Goodson and Mehdi Asheghi, ensures that the heat rising from the stacked layers of electronics does not degrade overall system performance.


Proof of principle

Mitra and Wong have already demonstrated a working prototype of a high-rise chip. At the International Electron Devices Meeting in December 2014 they unveiled a four-layered chip made up of two layers of RRAM memory sandwiched between two layers of CNTs.


In their N3XT paper they ran simulations showing how their high-rise approach was a thousand times more efficient in carrying out many important and highly demanding industrial software applications.


Stanford computer scientist and N3XT co-author Chris Ré, who recently won a “genius grant” from the John D. and Catherine T. MacArthur Foundation, said he joined the N3XT collaboration to make sure that computing doesn’t enter what some call a “dark data” era.


“There are huge volumes of data that sit within our reach and are relevant to some of society’s most pressing problems from health care to climate change, but we lack the computational horsepower to bring this data to light and use it,” Re said. “As we all hope in the N3XT project, we may have to boost horsepower to solve some of these pressing challenges.”




– Credit and Resource –


Provided by: Stanford University




Microchip Design Boosts Performance